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TRW-4432-433 433MHz雙向模組

TRW-4432-433是完全集成的高功率無線電模組,高性能收發器設計,在非常低的功耗下達到最大效率值。該模組主要用於ISM(工業,科學和醫學)和SRD(短距離設備),頻率波段420MHZ~450MHz,內制PA,輸出達+19dBm。可由SPI介面調整功率,彈性控制輸出功率,通過SPI接口控制,既可控制輸出及接收資料,且可讀出RF IC之溫度,以便及時了解本模組是否在工作溫度範圍內。

  • 型號: TRW-4432-433
  • Data Sheet: download
  • 頻率: 433MHz
  • 示範電路圖: download

APPEARANCE

產品外觀

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FEATURES

產品特色

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SPECIFICATION

產品規格


Worldwide 433 ISM band operation

0.123 to 256KBPs on air datarates

Ultra low power operation

Output power range +20 dBm Max

18.5 Ma receive, 85 Ma @ +20 dBm transmit

Low cost

Digital RSSI

FSK, GFSK, and OOK modulation

1.8 to 3.6V supply range

Temperature sensor and 8-bit ADC

Automatic packet handling

Auto packet transaction handling

TX and RX 64 byte FIFOs

On-chip crystal tuning

ParameterSymbolTest ConditionMinTypMaxUnit
Supply Voltage RangePower
1.833.6VV
Power DownPowerPower Down
15
Na
RX Mode CurrentReceiver1KBPS
18.5
Ma
TX Mode CurrentTransmitter20dBm

85Ma
RX SensitivityReceiver512bps 433MHz-121dBm

-dBm

PinNameI/ODescription
1AntennaInput/outputAntenna
2GNDGNDGround
3ANT RXInputControlled antenna switch, IF Receiver MODE IS High Voltage
4ANT TXInputControlled antenna switch, IF Transmitter MODE IS High Voltage
5VCCInput+1.8V to +3.6 V Supply Voltage Input to Internal Regulators
6GPIO0Digital I/O

General Purpose Digital I/O that may be configured through the registers to perform various functions
including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW,
AntDiversity control, etc. See the SPI GPIO Configuration Registers, Address 0Bh, 0Ch, and 0Dh for .more information.

7GPIO1Digital I/O
8GPIO2Digital I/O
9GNDGNDGround
10SDODigital OutputProvides a serial read back function of the internal control registers.
11SDIDigital InputThis pin provides the serial data stream for the 4-line
12SCLKDigital Input

Serial Clock Input.
digital input. This pin provides the serial data clock function for the
4-line serial data bus. Data is clocked into the RF CHIP on positive edge transitions

13nSELDigital Input

Serial Interface Select input. 0– VDD V digital input. This pin provides the Select/Enable function for the 4-line serial data bus. The signal is also used to signify burst read/write mode

14NIRQDigital Output

General Microcontroller Interrupt Status output. When the Si4430/31/32 exhibits anyone of the Interrupt
Events the nIRQ pin will be set low=0. Please see the Control Logic registers section for more information
on the Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading a corresponding
SPI Interrupt Status Registers, Address 03h and 04h. No external resistor pull-up is required,but it may be desirable if multiple interrupt lines are connected

15SDNDigital Input

Shutdown input pin. 0–VDD V digital input. SDN should be = 0 in all modes except Shutdown mode. When SDN =1 the chip will be completely shut down and the contents of the registers will be lost.

16GNDGNDGround
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